The present invention relates to a sampling timing recovering method, and to a sampling timing recovering circuit.
Digital communication systems generally rely on a synchronization word to separate a data frame or segment and to decode the data. In addition, the synchronization word in the data frame or segment is also relied on for sampling timing recovery normally completed by a step of detecting the synchronization word and a step of recovering the sampling timing.
As shown in FIG. 1, in a sampling timing recovery circuit structure, the synchronization word is detected by a correlator 11 comparing the difference between the stored synchronization word and the sampled portion of the incoming signal. The segment integrator 12 integrates to determine the similarity of every sampled data segment to the stored synchronization, and is a serial shift register having a length equal to that of the data segment. The synchronization word detector 13 locates a sampled data segment having a maximum value as the synchronization word to be found. The confidence counter 14 counts how many synchronization words have been detected. The phase detector 15 is used to detect the phase error of the sampled data segment. This phase error is processed by the Automatic Phase Control Low Pass Filter (APC LPF) 16 to adjust the voltage controlled crystal oscillator (VCXO) 17 for the purpose of phase locking.
FIG. 2 shows another sampling timing recovering circuit structure which differs from FIG. 1 in that a hard limiter 21 is provided before the correlator 11 for reducing the complexity of the circuit, which, nevertheless, is useful only for the particular synchronization word. Certainly, under such structure, the segment integrator 12 might be optional for a different circuit design according to the prior art.
In such prior sampling timing recovering circuits, all of them suffer from a common problem resulting from a symbol frequency error between the local sampling frequency of the analog-to-digital convertor and the input symbol rate (frequency) of the incoming signal. If the symbol frequency error is too large, it would be quite possible that the synchronization word is no longer detectible and the sampling timing is no longer recoverable in that there will be a too fast phase drift so that the segment integrator cannot so accumulate as to enable the confidence counter to finish counting. As an example, if there is a data frame having 1,000 symbols and if the frequency error is 100 ppm (parts per million), every entire frame will drift 0.1 symbol time (Ts). Specifically, if the phase detector can only detect the phase error in the range of +/xe2x88x9245 degrees, the phase detector can only detect two consecutive synchronization words, which are assumed to have a phase difference of 72 degrees in the above-mentioned example, so that the confidence counter, which normally counts more than 3, cannot finish its counting. Generally, the situation is more serious and worse. Even if the confidence counter can finish its counting, the phase might have drifted to the brim of the phase detecting range and continuously drifts. As a result, the phase has drifted out of the phase detecting range before the sampling timing recovering circuit can respond so that the operations of the synchronization word detection and the timing recovery must be performed again.
It is therefore attempted by the applicant to deal with the above situation encountered by the prior art.
It is therefore an object of the present invention to provide a method or a circuitry capable of facilitating the operation of the sampling timing recovering circuit.
It is further an object of the present invention to provide a sampling timing recovering method or circuit free from malfunction due to the frequency error.
It is still an object of the present invention to provide a sampling timing recovering method or circuit having a reduced frequency and a reduced phase error.
It is additionally an object of the present invention to provide a sampling timing recovering circuit or method with a better stability and a smaller phase jitter.
According to a first aspect of the present invention, a sampling timing recovering circuit includes a phase locking circuit having a local sampling frequency for processing an incoming signal having a phase, a specific parameter and an input symbol rate, and for locking the phase of said incoming signal, and a frequency locking circuit electrically connected to the phase locking circuit for locking the input symbol rate of the incoming signal to enable the phase locking circuit to process the incoming signal.
Preferably the present circuit further includes a synchronization word detecting circuit electrically connected to the phase locking circuit for detecting the specific parameter being a synchronization word, and a confidence counter circuit electrically connected to the synchronization word detecting circuit for identifying a location of the synchronization word and a frame number that the incoming signal requires to experience in the confidence counter circuit an entire cycle.
Certainly, the synchronization word can be assumed to be detected when a Boolean distance between a predetermined synchronization word and a sampled section of the incoming signal is found to be smaller than a predetermined value.
Certainly, the confidence counter circuit can be a dual loop confidence counter circuit which includes a detecting confirming circuit electrically connected to the synchronization word detecting circuit for confirming the synchronization word is detected, and a loss confirming circuit electrically connected to the detecting confirming circuit and initiated thereby when the synchronization word is confirmed to be detected by the detecting confirming circuit for initiating the detecting confirming circuit after the synchronization word is confirmed to be lost.
Certainly, we can assume that the synchronization word is confirmed to be detected when synchronization words in a specific number of consecutive data segments are all detected. By the same token, the synchronization word is confirmed to be lost when none of synchronization words in a specific number of consecutive data segments is detected.
Certainly, the frequency locking circuit can include a frequency error detecting circuit electrically connected to the confidence counter circuit and the phase locking circuit for generating, in response to the frame number, an initiating signal to be outputted to the phase locking circuit and a frequency error between the input symbol rate and the local sampling frequency, and a frequency compensating circuit electrically connected to the frequency error detecting circuit and the phase locking circuit for generating a frequency compensating voltage to be outputted to the phase locking circuit in response to the frequency error.
Certainly, the phase locking circuit can include an analog-to-digital converter electrically connected to the synchronization word detecting circuit for sampling and quantifying the incoming signal to be outputted to the synchronization word detecting circuit, a phase detecting circuit electrically connected to the analog-to-digital converter and the frequency error detecting circuit for detecting a phase error of the incoming signal to generate a phase compensating voltage in response to the initiating signal, and a voltage controlled oscillator electrically connected to the analog-to-digital converter, the phase detecting circuit and the frequency compensating circuit for generating, in response to the frequency compensating voltage and the phase compensating voltage, a clock having a specific phase and a specific frequency the same to those of the incoming signal to be outputted to the analog-to-digital converter for modifying the phase of the incoming signal and the local sampling frequency of the phase locking circuit.
In a practical instance, the frequency error can be a Doppler effect.
In an embodiment, the phase locking circuit processes the incoming signal into a digital signal.
In an example, the incoming signal has a data segment format and a segment synchronization word.
In a first application, the incoming signal can be used in a Advanced Television Systems Committee system.
In a second application, the incoming signal can be used in an Asymmetric Digital Subscriber Loop system.
In a third application, the incoming signal can be used in a European Digital Audio Broadcasting system.
In accordance with a second aspect of the present invention, a sampling timing recovering method includes the steps of a) processing an incoming signal having a phase, a specific parameter and an input symbol rate to have the phase lockable, (b) locking the input symbol rate of the incoming signal, and (c) locking the phase of the incoming signal to enable the incoming signal to be predeterminedly processed.
Preferably the present method further includes d) detecting the specific parameter being a synchronization word, and e) identifying a location of the synchronization word and a frame number that the incoming signal has been ascertainable.
Preferably the present method further includes f) generating, in response to the frame number, a frequency error between the input symbol rate and a local frequency, and g) generating a frequency compensating voltage in response to the frequency error.
Preferably the present method further includes i) detecting a phase error of the incoming signal to generate a phase compensating voltage, and generating, in response to the frequency compensating voltage and the phase compensating voltage, a clock having a specific phase and a specific frequency the same to those of the incoming signal for modifying the phase of the incoming signal and the local frequency.
The present invention may best be understood through the following descriptions with reference to the accompanying drawings, in which: